At-speedtestingusingexternaltesterrequiresanexpensiveequipment,thusbuilt-inself-test(BIST)isanalternativetechniqueduetoitsabilitytoperformon-chipat-speedself-testing.ThemainissueinBISTforat-speedtestingistoobtainhighdelayfaultcoveragewithalowhardwareoverhead.Thispaperpresentsanimprovedloop-basedBISTscheme,inwhichaconfigurableMISR(multiple-inputsignatureregister)isusedtogeneratetest-pairsequences.ThestructureandoperationmodesoftheBISTschemearedescribed.Thetopologicalpropertiesofthestate-transition-graphoftheproposedBISTschemeareanalyzed.Basedonit,anapproachtodesignandefficientlyimplementtheproposedBISTschemeisdeveloped.ExperimentalresultsonacademicbenchmarkcircuitsarepresentedtodemonstratetheeffectivenessoftheproposedBISTschemeaswellasthedesignapproach.
